Sigrity ™ SPEED2000 ™

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SPEED2000 Sigrity ™ SPEED2000 ™

Sigrity ™ SPEED2000 ™은 전체 IC package 및 Board design의 transient simulation을 수행할 수 있는 최초이자 유일한 상업적으로 이용 가능한 tool입니다. SPEED2000은 IBIS 모델을 통합 할 수 있으며 Signal & Power Integrity 및 design-stage EMI analysis를 위한 포괄적인 PCB/package layout 기반의 time domain EM 시뮬레이션 툴입니다. SPEED2000은 design sign-off와 debug를 해결하기 위한 layout 검사를 지원합니다.

  • :: Key Benefits
    • First and only commercially available transient simulation environment for package/board signal and power integrity
    • Single-step environment for comprehensive assessments without the need for model building
    • Direct time domain observation and confirmation of system performance to confirm specs are met
    • Superior accuracy enabled by advanced meshing and a combination of solvers to account for transmission line, circuit, and field effects
    • Fast what-if scenario support to assess targeted design improvements
    • Accurate handling of complex 3D structures such as wirebonds and vias
    • Flexible 2D and 3D results visualization options including waveforms and virtual walk-through
    • Unique electromagnetic control (EMC) simulation solution with support for designs with non-linear drivers and receivers
    • Optimized for flows with Cadence SiP Layout, Allegro Package Designer, and Allegro PCB Designer
    • Readily used in Mentor, Zuken, and Altium flows, accepting a mix of CAD databases where needed for multi-structure design support
  • :: Major Features
    • Performs time domain analysis to confirm that designs meet specified targets
    • Understands complex voltage noise propagation including return path discontinuities
    • Simulates simultaneous switching noise (SSN) and identifies improvement options
    • Assesses various decoupling capacitor implementations
    • Determines the impact of variations in stack-up, plane geometries, and I/O configurations
    • Identifies package and board resonance and radiation harmonics
    • Observes where noise is generated, identifies how it propagates, and determines if it stays within targeted levels
    • Provides streamlined workflows for layout-based DDR SSN simulation and layout-based electrical performance checks
    • Generates effective pre-layout guidelines and understands the impact of variances as the design progresses