IC DESIGN

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Digital IC Design ENCOUNTER Original IC DESIGN PLATFORM

The Cadence Encounter digital IC design platform provides the fastest route to very large-scale, high-performance chips. The Encounter¢ç platform covers a full spectrum nanometer-scale digital integrated circuit (IC) design flow£º synthesis, test equivalence checking, prototyping, signal integrity, routing, delay calculation, constraint management yield, power, and more.

SoC Encounter L is a full-function, netlist-to-GDSII configuration for flat designs of up to 5 million gates. This configuration has a flexible licensing model.

SoC Encounter XL is a full-Function, RTL-to-GDSII configuration for flat or hierarchical designs of more than 50 million gates.

SoC Encounter GXL is a full-function, RTL-to-GDSII configuration for advanced hierarchical designs of more than 100 million gates. Encounter digital IC design platform

 

  • SoC Encounter LSoC Encounter L is a full-function, netlist-to-GDSII configuration for flat designs of up to 5 million gates. This configuration has a flexible licensing model.
  • SoC Encounter XLSoC Encounter XL is a full-Function, RTL-to-GDSII configuration for flat or hierarchical designs of more than 50 million gates.
  • SoC Encounter GXLSoC Encounter GXL is a full-function, RTL-to-GDSII configuration for advanced hierarchical designs of more than 100 million gates.

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