Allegro Pakage Design

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Allegro Pakage Designer Physical layout and co-design

SiP and complex IC package design requires seamless integration between chip and package. Cadence® physical layout and co-design technology offers powerful modeling and simulation to enable informed design tradeoffs early.

Allegro Pakage Designer Integrates advanced package design with concurrent IC development. Analyzes physical, electrical, and cost tradeoffs early. Optimizes connectivity, routing, and SI using a constraint-driven methodology. Complete 3D co-design capabilities Allegro Package Designer provides true integration with IC development in a physical co-design environment to help engineers make strategic tradeoffs earlier and with greater confidence. Cadence® Allegro® Package Designer integrates with First Encounter® Silicon Virtual Prototyping to deliver chip-level I/O feasibility planning capabilities in an industry-proven co-design methodology. Data integration with First Encounter technology provides mask accuracy in the RDL routing and improves I/O padring optimization, substrate interconnect design, extraction, modeling, and signal integrity analysis. The final design output provides automatic

  • :: Features/Benefits
    • Supports a full front-to-back IC/package physical co-design flow
    • Determines the best package and substrate options early in the IC design cycle PCB design solution
    • Provides comprehensive design rule- and electrical constraint?driven layout Constraint-driven
    • Incorporates design for manufacturing (DFM) methodologies Constraint Management
    • Optimizes I/Os at the die bump level with a package-driven flow
    • Improves design flow with intrinsic support for all industry standards
    • Models entire design with Cadence 3D Design Viewer
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Allegro Pakage SI

Delivers a virtual prototyping design and simulation environment for IC packages using accurate 3D simulation models. Direct read/write from the design database provides fast, accurate models for critical design decisions. Virtual interconnect exploration and simulation Allegro Package SI offers powerful simulation for source synchronous and serial interfaces. The embedded 3D field solver resolves electrical issues early and performs extensive post-layout debugging. Cadence® Allegro® Package SI performs direct read/write to the design database to achieve accurate prototyping without time-consuming setup, and directly incorporates the results. By providing key indicators early in the design process, it helps engineers make difficult tradeoff decisions. A graphical topology simulator/editor allows engineers to compare different electrical routing strategies, optimize design rules, and develop S-Parameter models. Adding a partner-supplied Apache Design Solutions 3D field solver provides accurate extraction. Allegro Package SI can also be used as a plug-in for chip/package IR drop analysis when used in conjunction with VoltageStorm® Power Verification.

  • :: Features/Benefits
    • Streamlines virtual prototyping, interconnect exploration, analysis, and modeling
    • Performs topology editing and solution space exploration with SigXplorer
    • Determines the best substrate options early in the design cycle
    • Includes SPICE-based simulation
    • Allows integration with the Apache-DA PakSI-E 3D field solver
    • Provides hierarchical constraint management
    • Enables virtual substrate editing and post-layout debugging
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Cadence SiP Layout

Provides a complete constraint- and rules-driven substrate layout and interconnect environment. Includes 3D die stack creation/editing and comprehensive substrate DFM capabilities. Logical and physical co-design using 3D techniques Cadence SiP Digital Layout provides a complete constraint- and rules-driven co-design and substrate layout environment for SiP implementation, including full 3D creation and editing capabilities. Cadence® SiP Digital Layout is the physical co-design and place-and-route solution for complex 3D SiP package design. Supporting all package interconnect strategies and combinations, SiP Digital Layout provides constraint-driven layout of the package substrate. Since it must operate in a 3D world, SiP Digital Layout allows stack assembly optimization with 3D layout and editing. It also performs autoroute and breakout on flip-chip dies to reduce time-consuming and tedious manual breakout. Comprehensive DFM checking and modification improve substrate yield. Design review documentation and debug, followed by direct manufacturing tapeout, complete the package.

  • :: Features/Benefits
    • SReads Encounter® digital IC design technology databases
    • Includes embedded IC mask-ready I/O planning editor based on First Encounter® technology
    • Provides 3D die stack creation/editing for rapid stack assembly and optimization
    • Completes I/O padring/array co-design with multi-level optimizationn
    • Enables connectivity assignment to minimize layer usage based on SI analysis
    • Includes solid model 3D design viewer with snapshots for design review
    • Performs 3D wirebond verification and DRC
    • Supports bi-directional ECO and LVS flow for full co-design environment profiles
    • Includes a comprehensive suite of DFM preparation technologies
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Cadence SiP Digital SI

Integrates digital SI analysis and interconnect extraction using SPICE-based simulation and embedded integration of a third-party 3D field solver. Permits interactive editing of die-to-die and substrate interconnects. Virtual high-speed interconnect simulation Cadence SiP Digital SI offers a powerful simulation environment for source synchronous and serial interfaces. Integration with a 3D field solver resolves performance issues early and enables extensive post-layout debugging. Cadence® SiP Digital SI creates a co-simulation environment directly with the SiP design database to perform accurate signal prototyping and interconnect extraction without time-consuming setup and translation. A graphical topology simulator/editor allows engineers to compare different electrical routing strategies, optimize design rules, and develop S-Parameter models. Providing key indicators early in the design process helps make difficult cost/performance and physical/electrical design tradeoffs. Embedded integration with a separately supplied 3D field solver provides complex geometry extraction for accurate interconnect simulation.

  • :: Features/Benefits
    • Reads/writes Cadence SiP Digital Layout files
    • Streamlines virtual prototyping, interconnect exploration, analysis, and modeling
    • Provides fast, high-capacity simulation for multi-gigahertz interconnect analysis
    • Performs topology editing and solution space exploration
    • Includes SPICE-based simulation
    • Provides embedded integration with the Apache-DA PakSI-E 3D field solver
    • Provides hierarchical constraint management
    • Enables virtual substrate editing and post-layout debugging
    • Simplifies design debug and reviews with Cadence 3D Design Viewer