Sigrity ™ Product

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Sigrity Product Sigrity ™

첨단 기술 업체 들은 복잡한 칩, 패키지와 보드를 개발 중에 파워와 시그널 합성 이슈와 씨름하고 있고, 그것은 IC 스피드와 Data 전송율의 급격한 증가로 인한 것이며 이러한 일들은 공급 전압의 하향화와 높은 밀도, 좁은 면적과 연관되어 있습니다. 동시에 높은 I/O수, 다량의 칩과 패키지, 그리고 늘어나는 전기적 기능 요소 들로 인해 더 복잡한 물리적 설계가 필요하게 됩니다. 돌파구로 Cadence 솔루션을 만나면 특허 등록된 독점적인 Sigrity 기술을 기반으로 하여 이러한 개발과제 들을 극복할 수 있습니다. 이러한 솔루션 들의 목표는 칩, 패키지 그리고 보드에 걸쳐 있는 파워 전달 시스템 분석을 완벽하게 해주는 것이고, 시스템-레벨 신호 합성 (SI) 분석 뿐 아니라, 고속 신호 전송의 SSN 분석, 그리고 single and multi-chip 패키지, 최첨단 3D 패키지, SIP의 첨단 physical design을 완벽하게 분석해줍니다.

  • :: Sigrity Solution Overview

     

    • Broadband Model Extraction
    • Create broadband modles for time domain circuit simulation with full-wave solver accuracy models that are 2% of S-parameter model size.

       

       

    • Chip-Package-Board Modeling
    • Create Port for individual or grouped pins to achieve the desired level of abstraction when using models for either chip-centric or system-centric simulations.

       

       

    • Current Density / IR Drop
    • Rapidly identyfy hot spots in structures including vias,traces, planes, bond wires and solder balls to avoid hard-to-detect failures. Optimize sense line placement

       

       

    • Co-Design
    • Simultaneously simulate the entire chip power grid with the package / board in the time and frequency domain to find power integrity issues that are otherwise missed.

       

       

    • Decap Optimization
    • Assure power delivery system performance constraints are met while also targeting a decoupling scheme that is cost effective and conserves space.

       

       

    • EMI / EMC
    • Gain design stage visibility into potential hot spots with near and fer-field radiation studies to compliment signal and power integrity analysis.

       

       

    • High-Speed Interface Analysis
    • Effectively deal with parallel (DDR) and serial (PQ-E) design challenges by analyzing system-wide behavior using SSO and channel studies.

       

       

    • 10 Planning
    • Determine IO feasibility and assess imp4ementation options across chip, package and board designs utilizing data from each of these environments.

       

       

    • Package Layout
    • Create manufacturing ready designs incorporating wirebond or flip-chip attachment using e-driven techniques to assure electrical constraints are met

       

       

    • Power Integrity
    • Assure robust power delivery system performance and mitigate the impact of coupling between planes, traces, vias and other structures.

       

       

    • RLCC Extraction
    • Rapidly generate IBIS or SPICE RLCG single-stage models (including Pi or T circuits) for selected nets or entire designs that include coupling effects.

       

       

    • Signal Integrity
    • Analyze crosstalk, reflection, rise time degradation and related issues within a full system context to consider return path discontinuity with full wave accuracy.

       

       

    • SiP Analysis and Design
    • Extract modds for the ever increasing range of multi-die implementation configurations, analyze the effect of noisy components and quickly create design layouts.

       

       

    • S-parameter Extraction and Analysis
    • Achieve the highest possible model accuracy and understand the most complex spatial relationships for complete package and board designs.

       

       

    • SPICE Extraction and Analysis
    • Generate models for use with SPICE compatible circuit simulators and enable practical design flows that accurately reflect power / ground plane effects.

       

       

    • SSO / SSN
    • Simulate ground noise propagation due to switching current under predicted and worst case conditions in the time or frequency domain for design improvement.